1. Field of the Invention
The present invention relates to a semiconductor device for use in an image sensor and a method of manufacturing the semiconductor device.
2. Description of the Related Art
An image sensor is, for example, an array of cells each having a photodiode arranged in a plane. Typically, incident light enters a color filter or a prism, and is separated into light having a wavelength of a red band (R band), a green band (G band), and a blue band (B band). By directing the separated light to cells having the same structure, respectively, intensity of the incident light is detected with regard to the respective wavelengths of the R, G, and B bands. Another image sensor directs light having wavelengths of R, G, and B bands to the same cell in a time-sharing manner and detects intensity of incident light with regard to the respective wavelengths of R, G, and B bands for each divided time.
FIG. 1 illustrates a structure of a cell for a typical image sensor.
As illustrated in FIG. 1, a cell (a photodiode) of the image sensor has an n-type well 2 formed in a predetermined region of a p-type substrate 1, a field oxide film 3 formed by local oxidation of silicon (LOCOS) at an upper edge of the n-type well 2 for isolation, a heavily doped n-type region 4 for making electric connection with the n-type well 2, an interlayer insulating film 5 formed on the field oxide film 3, metal line 6 formed through the interlayer insulating film 5 and connected with the heavily doped n-type region 4, and a protective film 7 formed on the interlayer insulating film 5 and the metal line 6, for protecting the device. It should be noted that, as disclosed in JP 04-099066 A, there is another type of device in which isolation is performed by a trench insulating layer around one cell. In the cell having the above-mentioned structure, depletion layers K1 to K3 are generated in the vicinity of junction interfaces J1 to J3, respectively, between the p-type substrate 1 and the n-type well 2. When incident light 9 enters, light absorbed in the device causes generation of carriers 10 (electron-hole pairs). Movement of the carriers 10 generated mainly in the depletion layers K1 to K3 to the p-type region and the n-type region respectively generates electric current to perform photoelectric conversion.
As illustrated in FIG. 1, the junction interfaces J1 to J3 between the p-type substrate 1 and the n-type well 2 includes the junction interface J1 in parallel with a light incidence plane and the junction interfaces J2 and J3 perpendicular to the light incidence plane. The depletion layers K2 and K3 generated by the junction interfaces J2 and J3 are therefore regions which are disposed substantially in parallel with the incident light 9 in a depth direction of the p-type substrate 1. Consequently there are regions which greatly contribute to the photoelectric conversion and which do not contribute to the photoelectric conversion at all, that is, regions which greatly contribute to sensitivity of the device and which do not contribute to the sensitivity at all. Regarding a function as an electric circuit, since the depletion layers K1 to K3 work as capacitors C1 to C3, having a depletion layer which does not contribute to the sensitivity of the device means having an excess parasitic capacitance, which causes lowering of output voltage at the time of photoelectric conversion. This is obvious from the fact that, in the above-mentioned structure of the device, according to the relationship between voltage and capacitance (V=Q/C), an output voltage V lowers as a capacitance C increases. Therefore, in order to magnify the output voltage V, that is, in order to enhance the photoelectric conversion efficiency and the sensitivity of the device, it is desirable to increase an electric charge Q or to decrease the capacitance C.
As described above, there is a problem in that the output voltage cannot be raised in the photoelectric conversion since a cell having a conventional structure has excess capacitance. It should be noted that, in terms of decreasing the parasitic capacitance, JP 2004-040126 A discloses methods such as to devise a structure of a well itself. However, none of the methods focuses on the capacitances C2 and C3 of the depletion layers K2 and K3 formed on sides of the well. In particular, it is desirable to dispose the depletion layer K1 on a bottom side at a predetermined depth in order to perform the photoelectric conversion efficiently. However, in this case, not only the regions of the depletion layers K2 and K3 on the sides increases, but also the capacitances C2 and C3 of the depletion layers K2 and K3 increases, which is a large obstacle for efficient photoelectric conversion.
In particular, currently, with growing popularity in digital cameras and the like, an image sensor of higher resolution, that is, an image sensor having a larger number of pixels is desired. However, in order to make the number of pixels large without increasing the size of the image sensor as a whole, an area per cell needs to be made smaller, and thus, a semiconductor device with a small area per cell and yet with high photoelectric conversion efficiency is desired.